{"id":91299,"date":"2024-11-13T15:07:57","date_gmt":"2024-11-13T06:07:57","guid":{"rendered":"https:\/\/loco-staging.shoplic.site\/rebellions\/?p=91299"},"modified":"2025-02-16T17:27:22","modified_gmt":"2025-02-16T08:27:22","slug":"rebel-and-beyond-towards-a-unified-chiplet-ecosystem","status":"publish","type":"post","link":"https:\/\/loco-staging.shoplic.site\/rebellions?p=91299","title":{"rendered":"REBEL and Beyond \u2014 Towards a Unified Chiplet Ecosystem"},"content":{"rendered":"\n<p>As Moore\u2019s Law approaches its practical limits, chiplet architecture is gaining attention for its unique advantages: bypassing reticle constraints, nearly doubling time-to-market speed, and achieving higher yields with fewer defects per unit area compared to monolithic designs. This shift has spurred industry interest in building a robust ecosystem for standardized chiplets, such as high-speed I\/O or analog-to-digital converters. A thriving chiplet ecosystem would bring transformative benefits to chip manufacturers, end-users, and the entire semiconductor industry by fostering innovation, ensuring interoperability, and enhancing cost efficiency.<\/p>\n\n\n\n<p>As an active proponent of this ecosystem, Rebellions has mapped out a roadmap for future REBEL products, designed to embrace unified standards and interoperable IPs within the chiplet framework.<\/p>\n\n\n\n<p style=\"font-size: 0.85em;color: #666;font-style: italic\">* The designs are subject to change<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" style=\"margin-bottom: 12px\"><br>REBEL<\/h2>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img decoding=\"async\" width=\"920\" height=\"1024\" src=\"https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image-920x1024.png\" alt=\"\" class=\"wp-image-91485\" style=\"width:840px;height:auto\" srcset=\"https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image-920x1024.png 920w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image-269x300.png 269w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image-768x855.png 768w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image-1380x1536.png 1380w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image-640x713.png 640w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image.png 1517w\" sizes=\"(max-width: 920px) 100vw, 920px\" \/><\/figure>\n\n\n\n<p>REBEL is Rebellions\u2019 chiplet-based AI accelerator engineered specifically for data center-scale workloads. Designed from the ground up for exceptional efficiency, high hardware utilization, low latency, and seamless scalability, REBEL sets a new standard in AI performance.<\/p>\n\n\n\n<p>Equipped with 144GB of <strong>HBM3e<\/strong> memory, it delivers an impressive 1 PFLOPS of FP16 compute power within a 350W power envelope.&nbsp;REBEL also leverages the <strong>UCIe-Advanced specification<\/strong> for ultra-high bandwidth density, near-zero latency, and remarkable energy efficiency. Following REBEL, Rebellions is introducing advanced derivatives that leverage its chiplet-based architecture for seamless heterogeneous integration. These solutions add I\/O dies, enhanced memory capacity, and integrated CPU functionality, further extending the REBEL architecture with specialized options for diverse AI infrastructure needs.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" style=\"margin-bottom: 12px\"><br>REBEL-I\/O<\/h2>\n\n\n\n<figure class=\"wp-block-image size-large\"><img decoding=\"async\" width=\"1024\" height=\"703\" src=\"https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/Screenshot-2025-02-16-at-5.25.58\u202fPM-1024x703.png\" alt=\"\" class=\"wp-image-91489\" srcset=\"https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/Screenshot-2025-02-16-at-5.25.58\u202fPM-1024x703.png 1024w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/Screenshot-2025-02-16-at-5.25.58\u202fPM-300x206.png 300w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/Screenshot-2025-02-16-at-5.25.58\u202fPM-768x527.png 768w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/Screenshot-2025-02-16-at-5.25.58\u202fPM-640x439.png 640w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/Screenshot-2025-02-16-at-5.25.58\u202fPM.png 1366w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>REBEL-I\/O introduces dedicated interface dies that handle data communication between multiple processing chips. By offloading peripheral functions to the I\/O Ethernet interface, the main chiplet dies can focus exclusively on computation and significantly enhance its power.&nbsp;<\/p>\n\n\n\n<p>This modular approach mitigates manufacturing challenges: unlike monolithic chips, REBEL-I\/O allows components with distinct process node requirements to be fabricated independently, promoting reuse and cutting cost. Additionally, the Ethernet interface offers future-proof scalability for both chip-to-chip (scale-up) and server-to-server (scale-out) connectivity, with far less communication overhead, enabling seamless expansion as demands grow.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" style=\"margin-bottom: 12px\"><br>REBEL-CPU<\/h2>\n\n\n\n<figure class=\"wp-block-image size-full\"><img decoding=\"async\" width=\"758\" height=\"996\" src=\"https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image-2.png\" alt=\"\" class=\"wp-image-91487\" srcset=\"https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image-2.png 758w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image-2-228x300.png 228w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/image-2-640x841.png 640w\" sizes=\"(max-width: 758px) 100vw, 758px\" \/><\/figure>\n\n\n\n<p>While a single chiplet in REBEL contains a CPU, REBEL-CPU goes further by heterogeneously integrating Arm\u2019s 64-core CPU cluster Compute Subsystem (CSS). This improves resource utilization by allowing the main chiplet to focus exclusively on workload acceleration.<\/p>\n\n\n\n<p>The synergy between CPU and accelerators enables each component to operate at peak efficiency, maximizing compute power and minimizing latency as systems scale across servers and racks. This integration delivers up to 10x higher efficiency in server and rack-level solutions, and also lays the optimal foundation for AI training.With planned support for reliability, availability, and serviceability (RAS) features, REBEL-CPU is positioned as a robust solution for demanding AI applications.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" style=\"margin-bottom: 12px\"><br>REBEL-MEM<\/h2>\n\n\n\n<figure class=\"wp-block-image size-full\"><img decoding=\"async\" width=\"682\" height=\"1004\" src=\"https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/Screenshot-2025-02-16-at-5.26.26\u202fPM.png\" alt=\"\" class=\"wp-image-91490\" srcset=\"https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/Screenshot-2025-02-16-at-5.26.26\u202fPM.png 682w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/Screenshot-2025-02-16-at-5.26.26\u202fPM-204x300.png 204w, https:\/\/loco-staging.shoplic.site\/rebellions\/wp-content\/uploads\/2025\/02\/Screenshot-2025-02-16-at-5.26.26\u202fPM-640x942.png 640w\" sizes=\"(max-width: 682px) 100vw, 682px\" \/><\/figure>\n\n\n\n<p class=\"has-text-align-center\"><\/p>\n\n\n\n<p>Recognizing the increasing memory demands driven by growing model sizes, REBEL-MEM is designed to enhance REBEL\u2019s memory capacity through additional external memory dies. This added memory, combined with HBM3e\u2019s industry-leading bandwidth, ensures REBEL can meet the challenges for any large-scale AI workloads.<\/p>\n\n\n\n<p>With an external memory expander, REBEL-MEM gains up to 300GB\/s bandwidth and 200GB additional capacity via LPDDR or GDDR memory. This enables the chiplet to efficiently handle memory-centric AI models, namely LLMs, Video Language Models (VLMs), and Deep Learning Recommendation Models (DLRMs). These applications have substantial memory requirements due to large model sizes, extended sequence lengths, or significant intermediate data storage.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" style=\"margin-bottom: 12px\"><br>Stay tuned!<\/h2>\n\n\n\n<p>Rebellions is developing innovative chiplets\u2013including REBEL, REBEL-I\/O, REBEL-CPU, and REBEL-MEM\u2013that are inline with our roadmap, pushing the next frontier in chiplet architecture. We will continue to pave the way to simplify integration complexity and drive cost-efficient, scalable AI acceleration, with highly interoperable, industry-leading solutions that set new standards in AI performance and affordability.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>As Moore\u2019s Law approaches its practical limits, chiplet architecture is gaining attention for its unique advantages: bypassing reticle constraints, nearly&#8230;<\/p>\n","protected":false},"author":8,"featured_media":91431,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"content-type":"","footnotes":""},"categories":[119],"tags":[],"class_list":["post-91299","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-highlights"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v24.8 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>REBEL and Beyond \u2014 Towards a Unified Chiplet Ecosystem - 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